In modern mobile communications systems the designer has the task of balancing user require- ments of high data throughputs with the cost concerns of low power consumption and imple- mentation costs. One important aspect of such systems is the forward error correction (FEC) coding employed to ensure reliable communication. In the receiver side of a mobile commu- nications system-on-a-chip (SoC) the FEC decoding contributes a significant part of design complexity. Unfortunately, there exist a multitude of FEC schemes which are deployed in to- day’s communication standards to deal with different application scenarios and these schemes often are implemented in separate IP blocks in a SoC. In accordance with the above mentioned goals of low power and slim implementation it is attractive to try and combine the decoding functionality for several FEC schemes into one IP block.
This work presents a framework of methods and rules that can be applied to execute such a merging of several decoding schemes. One part of this is analyzing target algorithms in their two main aspects communication and processing and the other applying findings from this anal- ysis on different hierarchical levels to determine the applicable methods of decoder merging. Furthermore, the proposed concepts are put into practice through the design of a multi-mode FEC decoder capable of decoding convolutional, turbo and LDPC codes to demonstrate appli- cation of the merging methods in different design steps to reach the final decoder realization. At a post-synthesis area of 0.77 mm2 the decoder reaches throughputs of 23.1 to 86.4 Mbps at a 200 MHz clock frequency, showing that it is on par with published works and therefore proving that the presented method can be used to produce state-of-the-art results. The decoder has also been implemented in silicon using a 65nm TSMC process, providing useful measurements to verify simulation results.
Another main topic of this work is the assessment of merging efficiency, a point that has been neglected so far in literature. To this end, single-mode decoders specialized on decoding just one type of codes - either Viterbi, Turbo or LDPC - are derived from the multi-mode architec- ture. Comparisons between multi-mode and single-mode decoders indicate that the former has a smaller overall area but suffers from an increase in dissipated power.