Suche ›

Reliability Aware High-Level Embedded System Design in Presence of Hard and Soft Errors

49,80 € Preisreferenz Lieferbar in 2-3 Tagen


Following the prediction of Moore’s Law the exponentially shrinking feature size has greatly increased both the processing as well as the memory resources. However, the amount of charge required to change the output of a digital circuit is becoming smaller, thereby making them more vulnerable to soft errors. In addition, the various layers of silicon in the transistor and the metal connecting them can now be measured in terms of the number of atoms, and therefore are greatly vulnerable to high temperatures and voltages. This has caused a decline in the hard errors in digital circuits due to the improvement in technology to be halted. Therefore, modeling reliability of digital devices both the soft as well as the hard errors occurring in the digital resources must be considered. In addition, the digital processing resources should be considered as fail non-silent.
Nevertheless, the increase in processing and memory resources is being used to improve the present digital systems as well as to construct ones that are more complex. The use of digital resources as embedded systems are becoming more pervasive in diverse application domains such as automotive, avionic, medical, control, as well as common everyday applications ranging from wristwatch to cell phones. The safety critical system must be highly reliable and some minimum reliability for non-safety critical application should also be guarantied. Due to increasing complexity of the systems, it is no longer possible to design them at lower levels of abstraction. Designing for reliability in the latter stages of the design phase may lead to a complete redesign of the system in the worst case, or can be very costly. This means that reliability aspects must be considered simultaneously along with the other parameters of the system (e.g., execution time and energy consumption) during the earlier part of the design process.
A system-level design process of reliable systems demands efficient reliability evaluation of the explored design alternatives. This dissertation presents a new approach to accelerate calculation of the reliability, execution time, and energy consumption of the system and thereby the design space exploration for reliable systems. A new data structure denoted as System Error Decision Diagram (SEDD) is proposed, which is based on both binary decision diagrams to model hard errors and zero-suppressed decision diagrams to model soft errors. The construction of the SEDD diagram and calculation the reliability based on it are both detailed in an algorithmic way. In addition, a set of data structures termed as Split System Decision Diagrams are presented. These diagrams comprise of a couple of new data structures denoted as System Resource Decision Diagram and System Task Instance Decision Diagram, respectively, which are based on the zero-suppressed decision diagram. The first data structure deals with hard errors occurring in the system, whereas the second one represents the effects soft errors have on the system’s functionality. Both the construction of this diagram pair and the memory-aware calculation of the system attributes based on it, with reliability being the focus, are detailed in an algorithmic way. The evaluation algorithms based on these data structure are slower than the ones based on the SEDD. Nevertheless, these data structures are much more memory efficient as compared to their counterpart the SEDD.
Using these efficient data structures and the corresponding algorithms, three types of design space algorithms were constructed.
1. System designed for the lifetime reliability and execution time
2. System designed for the lifetime reliability and energy consumption
3. System designed for the lifetime reliability, execution time, and energy consumption
The result of these design space exploration algorithm is a set of Pareto design alternatives. A so-called ‘human designer’ is thus able to best select one of the alternatives that best represents the given system requirement.
In order to evaluate and validate the developed methods and techniques presented in the dissertation, extensive experiments have been performed. Throughout the dissertation, the ideas and concepts are illustrated using a real-life automotive example (where these techniques were actually validated). These concepts are embodied in a computer aided engineering tool developed for the support of the advocated system level design approach.


Titel: Reliability Aware High-Level Embedded System Design in Presence of Hard and Soft Errors
Autoren/Herausgeber: Adeel Israr
Aus der Reihe: Berichte aus der Informatik
Ausgabe: 1., Aufl.

ISBN/EAN: 9783844010602

Seitenzahl: 238
Format: 21 x 14,8 cm
Produktform: Buch
Gewicht: 356 g
Sprache: Englisch - Newsletter
Möchten Sie sich für den Newsletter anmelden?

Bitte geben Sie eine gültige E-Mail-Adresse ein.
Lieber nicht